EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
Design-Reuse

Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC

CAMPBELL, Calif., October 16, 2008-- Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, announces the availability of their Gigabit ...
EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.