EDN

Guidelines for complex SoC verification

Almost 60-70% of time in the ASIC cycle is occupied by Functional Verification and so, the main aim of this paper is to provide overall guidelines in verification. More specifically, on the adoption ...
EDN

SoC Functional verification flow

This paper presents SoC- (System on Chip) level functional verification flow. It also describes ways to speed up the process. To ensure successful tapeout of SoCs, here are the steps of a standard SoC ...
Nasdaq

Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications

Samsung Foundry and Synopsys' optimized flow achieves predictable execution of in-system test, implementation, verification, timing and physical signoff for ASIL D-compliant SoC design Includes ...
Yahoo Finance

Breker Verification Systems and Moores Lab AI Partner to Create First AI-Driven SoC Verification Solution

SAN JOSE, Calif., Feb. 26, 2026 (GLOBE NEWSWIRE) -- Breker Verification Systems and Moores Lab AI today formalized a partnership to create the first AI-driven SoC verification flow integrating ...
Design-Reuse

Is Test Software Automation Imperative in SoC Verification?

A recent post on Cadence's Interconnect Workbench (ICW) caught my attention. ICW is a tool targeted toward the growing and evolving SoC verification market. Interconnect buses like AXI, AHB, and ...
Semiconductor Engineering

Crossing The Chasm: Uniting SoC And Package Verification

Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, ...
Nasdaq

NSITEXE Adopts Synopsys Design, Verification and IP Solutions to Accelerate the Development of New Processor Chip

MOUNTAIN VIEW, Calif., Sept. 3, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that NSITEXE, Inc. achieved success with its first silicon for Data Flow Processor (DFP)-based SoC ...
Electronic Design

SoC Test System Speeds Design Verification, Cuts Test Cost

As System-On-A-Chip complexity increases, testing the millions of gates that get integrated on the chip has become an ever more challenging and more expensive task. On-chip test support logic and ...
Semiconductor Engineering

Top-Down SoC Verification

In the world of system-on-chip (SoC) verification, 2014 was an interesting year of transition. After much discussion throughout the year about graph-based techniques and the role of software for ...
Design-Reuse

SoC interconnect performance verification methodology based on hardware emulator

This paper describes an interconnect performance verification methodology which was developed for a complex multi source digital television SoC project. The historical and technical reasons of the ...
Embedded

Dealing with SoC hardware/software design complexity with scalable verification methods

The problem with today's existing methodologies is that verification issubservient to design. This principle requires a shift in paradigm,especially in designing complex electronic systems. Why?
Electronic Design

What’s the Deal with SoC Verification?

The title of this article may sound like the start of a Seinfeld joke from the 90s, but it’s actually a serious question. Many people do not appreciate what makes a system-on-chip (SoC) different from ...